Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
Simultaneous routing and buffer insertion with restrictions on buffer locations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A hybrid dynamic/quadratic programming algorithm for interconnect tree optimization
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A fast algorithm for context-aware buffer insertion
Proceedings of the 37th Annual Design Automation Conference
Maze routing with buffer insertion and wiresizing
Proceedings of the 37th Annual Design Automation Conference
Routing tree construction under fixed buffer locations
Proceedings of the 37th Annual Design Automation Conference
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Buffer insertion with adaptive blockage avoidance
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 2002 international symposium on Physical design
S-Tree: a technique for buffered routing tree synthesis
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
Porosity aware buffered steiner tree construction
Proceedings of the 2003 international symposium on Physical design
Simultaneous Routing and Buffer Insertion for High Performance Interconnect
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Steiner tree optimization for buffers, blockages, and bays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A practical repeater insertion flow
Proceedings of the 18th ACM Great Lakes symposium on VLSI
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In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs to be performed on thousands of nets within an integrated physical synthesis system. In most of previous works, buffers may be inserted at any open space. Even when there may appear to be space for buffers in the alleys between large blocks, these regions are often densely packed or may be useful later to fix critical paths. In addition, a buffer solution may inadvertently force wires to go through routing congested regions. Therefore, within physical synthesis, a buffer insertion scheme needs to be aware of both placement congestion and routing congestion of the existing layout and so it has to be able to decide when to insert buffers in dense regions to achieve critical performance improvement and when to utilize the sparser regions of the chip. With the proposed Steiner tree adjustment technique, this work aims at finding congestion-aware buffered Steiner trees. Our tree adjustment technique takes a Steiner tree as input, modifies the tree and simultaneously handles the objectives of timing, placement and routing congestion. To our knowledge, this is the first study which simultaneously considers these three objectives for the buffered Steiner tree problem. Experimental results confirm the effectiveness of our algorithm while it achieves up to 20 × speed-up when comparing with the state-of-the-art algorithm [5].