RC interconnect optimization under the Elmore delay model
DAC '94 Proceedings of the 31st annual Design Automation Conference
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing for interconnects with multiple sources
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal non-uniform wire-sizing under the Elmore delay model
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An efficient approach to simultaneous transistor and interconnect sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Simultaneous buffer and wire sizing for performance and power optimization
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A new approach to simultaneous buffer insertion and wire sizing
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Buffer insertion with accurate gate and interconnect delay computation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
A polynomial time optimal algorithm for simultaneous buffer and wire sizing
Proceedings of the conference on Design, automation and test in Europe
Buffered Steiner trees for difficult instances
Proceedings of the 2001 international symposium on Physical design
A fast and accurate delay estimation method for buffered interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
On finding an empty staircase polygon of largest area (width) in a planar point-set
Computational Geometry: Theory and Applications
Power macromodeling of global interconnects considering practical repeater insertion
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Practical repeater insertion for low power: what repeater library do we need?
Proceedings of the 41st annual Design Automation Conference
A place and route aware buffered Steiner tree construction
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A sensitivity analysis of low-power repeater insertion
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Proceedings of the 42nd annual Design Automation Conference
Accurate estimation of global buffer delay within a floorplan
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Closed form solution for optimal buffer sizing using the Weierstrass elliptic function
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Efficient generation of short and fast repeater tree topologies
Proceedings of the 2006 international symposium on Physical design
Low-power repeater insertion with both delay and slew rate constraints
Proceedings of the 43rd annual Design Automation Conference
Hierarchical partitioning of VLSI floorplans by staircases
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Fast buffering for optimizing worst slack and resource consumption in repeater trees
Proceedings of the 2009 international symposium on Physical design
NANOARCH '09 Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures
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