RC interconnect synthesis—a moment fitting approach
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RC interconnect optimization under the Elmore delay model
DAC '94 Proceedings of the 31st annual Design Automation Conference
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wiresizing for interconnects with multiple sources
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimal wire-sizing formula under the Elmore delay model
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Optimal wiresizing under Elmore delay model
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal wire-sizing function with fringing capacitance consideration
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
A new approach to simultaneous buffer insertion and wire sizing
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
Greedy wire-sizing is linear time
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
A polynomial time optimal algorithm for simultaneous buffer and wire sizing
Proceedings of the conference on Design, automation and test in Europe
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Shaping a VLSI Wire to Minimize Elmore Delay
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design and verification of high-speed VLSI physical design
Journal of Computer Science and Technology
Self-heating-aware optimal wire sizing under Elmore delay model
Proceedings of the conference on Design, automation and test in Europe
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
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We consider non-uniform wire-sizing for general routing trees under the Elmore delay model. Three minimization objectives are studied: (1) total weighted sink-delays; (2) total area subject to sink-delay bounds; and (3) maximum sink delay. We first present an algorithm NWSA-wd for minimizing total weighted sink-delays based on iteratively applying the wire-sizing formula. We show that NWSA-wd always converges to an optimal wire-sizing solution. Based on NWSA-wd and the Lagrangian relaxation technique, we obtained two algorithms NWSA-db and NWSA-md which can optimally solve the other two minimization objectives. Experimental results show that our algorithms are efficient both in terms of runtime and storage. For example, NWSA-wd, with linear runtime and storage, can solve a 6201-wire segment routing-tree problem using about 1.5-second runtime and 1.3-MB memory on an IBM RS/6000 workstation.