Analytical Bound for Unwanted Clock Skew due to Wire Width Variation

Authors:
Anand Rajaram;Bing Lu;Wei Guo;Rabi Mahapatra;Jiang Hu
Affiliations:
Texas A&M University;Cadence Design Sys. Inc., New Providence, NJ;Institut Français du Pétrole, France;Texas A&M University;Texas A&M University
Venue:
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Year:
2003

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Abstract

Under modern VLSI technology, process variations greatly affectcircuit performance, especially clock skew which is very timingsensitive. Unwanted skew due to process variation forms a bottleneckpreventing further improvement on clock frequency. Impactfrom intra-chip interconnect variation is becoming remarkable andis difficult to be modeled efficiently due to its distributive nature.Through wire shaping analysis, we establish an analytical boundfor the unwanted skew due to wire width variation which is thedominating factor among interconnect variations. Experimental resultson benchmark circuits show that this bound is safer, tighterand computationally faster than similar existing approach.