Optimal wire-sizing function with fringing capacitance consideration
DAC '97 Proceedings of the 34th annual Design Automation Conference
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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In this paper, we consider non-uniform wire-sizing under the Elmore delay model. Given a wire segment, let f(x) be the width of the wire at position x. It was shown in [2,4] that the optimal wire-sizing function f which minimizes delay is an exponential tapering function. Unfortunately, [2,4] did not consider fringing capacitance which is at least comparable in size to area capacitance in deep submicron designs. As a result, exponential tapering is no longer the optimal strategy. In this paper, we show that the optimal wire-sizing function, taking fringing capacitance into consideration, can again be analytically determined. Experimental results show that the optimal wire-sizing function can significantly reduce the interconnection delay of exponentially tapered wires. In the case where lower and upper bounds on the wire widths are given, the optimal wire-sizing function is a truncated version of the above function. Finally, our optimal wire-sizing function can be iteratively applied to optimally size all the wire segments in a routing tree for objectives such as minimizing weighted sink delay, minimizing maximum sink delay, or minimizing area subject to delay bounds at the sinks.