Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect

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ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Year:
1997

Citing 0
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Abstract

In this paper, we describe a novel methodology for obtaining statistically-based worst case (i.e. 3-sigma) R (resistance), C (capacitance), and delay given variations in interconnect-related process parameters. Our approach is based on a weighted root-sum square method to derive 3-sigma C. A Monte Carlo-based method is used for the generation of 3-sigma R as well as randomized distributed RC nets to obtain realistic 3-sigma delays for long interconnect nets such as global critical paths. Using this methodology for a long critical net analysis on a 0.35um process, a more than 70% improvement in 3-sigma delay estimation compared with the traditional skew-corner worst case delay can be realized.