Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
JiffyTune: circuit optimization using time-domain sensitivities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A capacitance solver for incremental variation-aware extraction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An efficient resistance sensitivity extraction algorithm for conductors of arbitrary shapes
Proceedings of the 46th Annual Design Automation Conference
Efficient sensitivity-based capacitance modeling for systematic and random geometric variations
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Recent CAD methodologies of Design-for-Manufacturability (DFM) have naturally led to a significant increase in the number of process and layout parameters that have to be taken into account in design-rule checking. Methodological consistency requires that a similar number of parameters be taken into account during layout parasitic extraction. Because of the inherent variability of these parameters, the issue of efficiently extracting deterministic parasitic sensitivities with respect to such a large number of parameters must be addressed. In this paper, we tackle this very issue in the context of capacitance sensitivity extraction. In particular, we show how the adjoint sensitivity method can be efficiently integrated within a finite-difference (FD) scheme to compute the sensitivity of the capacitance with respect to a large set of BEOL parameters. If np is the number of parameters, the speedup of the adjoint method is shown to be a factor of np/2 with respect to direct FD sensitivity techniques. The proposed method has been implemented and verified on a 65nm BEOL cross section having 10 metal layers and a total number of 59 parameters. Because of its speed, the method can be advantageously used to prune out of the CAD flow those BEOL parameters that yield a capacitance sensitivity less than a given threshold.