Efficient statistical capacitance variability modeling with orthogonal principle factor analysis
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
Impact of line-edge roughness on resistance and capacitance of scaled interconnects
Microelectronic Engineering
Variational capacitance modeling using orthogonal polynomial method
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 45th annual Design Automation Conference
Variational capacitance extraction of on-chip interconnects based on continuous surface model
Proceedings of the 46th Annual Design Automation Conference
Rapid method to account for process variation in full-chip capacitance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a highly efficient sensitivity-based method for capacitance extraction, which models both systematic and random geometric variations. This method is applicable for BEM-based Layout Parasitic Extraction (LPE) tools. It is shown that, with only one system solve, the nominal parasitic capacitances as well as its relative standard deviations caused by both systematic and random geometric variations can be obtained. The additional calculation for both variations can be done at a very modest computational time, which is negligible compared to that of the standard capacitance extraction without considering any variation. Specifically, using the proposed method, experiments and a case study have been analyzed to show the impact of the random variation on the capacitance for a real design.