Galerkin Projection Methods for Solving Multiple Linear Systems
SIAM Journal on Scientific Computing
Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
High-Order Collocation Methods for Differential Equations with Random Inputs
SIAM Journal on Scientific Computing
Recycling Krylov Subspaces for Sequences of Linear Systems
SIAM Journal on Scientific Computing
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Proceedings of the 45th annual Design Automation Conference
A precorrected-FFT method for electrostatic analysis of complicated 3-D structures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ARMS - automatic residue-minimization based sampling for multi-point modeling techniques
Proceedings of the 46th Annual Design Automation Conference
A hierarchical floating random walk algorithm for fabric-aware 3D capacitance extraction
Proceedings of the 2009 International Conference on Computer-Aided Design
SPARE: a scalable algorithm for passive, structure preserving, parameter-aware model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
On process-aware 1-D standard cell design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
GPU-friendly floating random walk algorithm for capacitance extraction of VLSI interconnects
Proceedings of the Conference on Design, Automation and Test in Europe
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Lithographic limitations and manufacturing uncertainties are resulting in fabricated shapes on wafer that are topologically equivalent, but geometrically different from the corresponding drawn shapes. While first-order sensitivity information can measure the change in pattern parasitics when the shape variations are small, there is still a need for a high-order algorithm that can extract parasitic variations incrementally in the presence of a large number of simultaneous shape variations. This paper proposes such an algorithm based on the well-known method of floating random walk (FRW). Specifically, we formalize the notion of random path sharing between several conductors undergoing shape perturbations and use it as a basis of a fast capacitance sensitivity extraction algorithm and a fast incremental variational capacitance extraction algorithm. The efficiency of these algorithms is further improved with a novel FRW method for dealing with layered media. Our numerical examples show a 10X speed up with respect to the boundary-element method adjoint or finite-difference sensitivity extraction, and more than 560X speed up with respect to a non-incremental FRW method for a high-order variational extraction.