A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects

Authors:
Ying Zhou;Zhuo Li;Yuxin Tian;Weiping Shi;Frank Liu
Affiliations:
Department of Electrical Engineering, Texas A&MUniversity, College Station, Texas 77843;Pextra Corporation, 2900B Longmire Drive, College Station, Texas 77845;Department of Electrical Engineering, Texas A&MUniversity, College Station, Texas 77843;Department of Electrical Engineering, Texas A&MUniversity, College Station, Texas 77843;IBM Austin Research Laboratory, 11501 Burnet Rd., Austin, Texas 78758
Venue:
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Year:
2007

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Abstract

Even with the wide adaptation of resolution enhancement techniques in sub-wavelength lithography, the geometry of the fabricated interconnect is still quite different from the drawn one. Existing Layout Parasitic Extraction (LPE) tools assume perfect geometry, thus introducing significant error in the extracted parasitic models, which in turn cases significant error in timing verification and signal integrity analysis. Our simulation shows that the RC parasitics extracted from perfect GDS-II geometry can be as much as 20% different from those extracted from the post litho/etching simulation geometry. This paper presents a new LPE methodology and related fast algorithms for interconnect parasitic extraction under photo-lithographic effects. Our methodology is compatible with the existing design flow. Experimental results show that the proposed methods are accurate and efficient.