Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Bounded-skew clock and Steiner routing under Elmore delay
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A general probabilistic framework for worst case timing analysis
Proceedings of the 39th annual Design Automation Conference
Worst case clock skew under power supply variations
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Analytical Bound for Unwanted Clock Skew due to Wire Width Variation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A fast heuristic algorithm for multidomain clock skew scheduling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we address the problem of estimating clock-skew bounds in presence of power supply and process variations. We present a novel technique based on sequence of linear programs to compute the upper and lower bounds of clock skew. We apply our method to pairs of sinks between which logic paths in the circuit exist. When spatial correlations of process variations are known, our method provides more accurate results which reflect the real design. We use accurate models and time-domain analysis ts calculate the clock network delay and delay sensitivity. The experimental results demonstrate that our technique is capable of providing very accurate skew bounds estimation (within 10% error as compared to Monte-Carlo method) in acceptable run-times.