Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
IEEE Transactions on Computers
Buffer insertion and sizing under process variations for low power clock distribution
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Clock skew optimization for peak current reduction
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Useful-Skew Clock Routing with Gate Sizing for Low Power Design
Journal of VLSI Signal Processing Systems - Special issue on high performance clock distribution networks
Bounded-skew clock and Steiner routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Graph algorithms for clock schedule optimization
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Current signature compression for IR-drop analysis
Proceedings of the 37th Annual Design Automation Conference
UST/DME: a clock tree router for general skew constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock skew verification in the presence of IR-drop in the power distribution network
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Clock skew bounds estimation under power supply and process variations
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Minimizing peak current via opposite-phase clock tree
Proceedings of the 42nd annual Design Automation Conference
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Opposite-Phase Clock Tree for Peak Current Reduction
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Non-uniform clock mesh optimization with linear programming buffer insertion
Proceedings of the 47th Design Automation Conference
Power-driven flip-flop merging and relocation
Proceedings of the 2011 international symposium on Physical design
Simultaneous clock and data gate sizing algorithm with common global objective
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
High-performance clock mesh optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
In-placement clock-tree aware multi-bit flip-flop generation for power optimization
Proceedings of the International Conference on Computer-Aided Design
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In this paper, we investigate the problem of buffer sizing for clock power minimization subject to general skew constraints. A novel approach based on sequential linear programming is presented. By taking the first-order Taylor's expansion of clock path delay with respect to buffer widths, the original nonlinear problem is transformed to a sequence of linear programs, which incorporate clock skew scheduling and buffer sizing to minimize clock power dissipation. For each linear program, the sensitivities of clock path delay with respect to buffer widths are efficiently updated by applying time-domain analysis to the clock network in a divide-and-conquer fashion. Our approach can take process variations and power supply noise into account. We demonstrate experimentally that the proposed technique is not only capable of effectively reducing clock power consumption, but also able to provide more accurate delay and skew results compared to the traditional approach.