Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
MeshWorks: an efficient framework for planning, synthesis and optimization of clock mesh networks
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Ispd2009 clock network synthesis contest
Proceedings of the 2009 international symposium on Physical design
Analysis of high-performance clock networks with RLC and transmission line effects
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Proceedings of the 2011 international symposium on Physical design
Distributed Resonant clOCK grid Synthesis (ROCKS)
Proceedings of the 48th Design Automation Conference
Novel binary linear programming for high performance clock mesh synthesis
Proceedings of the International Conference on Computer-Aided Design
High-performance clock mesh optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Clock mesh synthesis with gated local trees and activity driven register clustering
Proceedings of the International Conference on Computer-Aided Design
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Multi-corner multi-voltage domain clock mesh design
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. However, this robustness costs power. In this work, we present a mesh edge displacement algorithm that is able to reduce mesh wire length by 7.6% and overall power by 10.5% with a small mean skew improvement. We also present the first non-greedy buffer placement and sizing technique using linear programming (LP) and iterative buffer removal. We show that compared to prior methods, we can obtain 41% power reduction and an 27ps mean skew reduction on average when variation is considered compared to prior algorithms.