Sizing of clock distribution networks for high performance CPU chips
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Process-induced skew reduction in nominal zero-skew clock trees
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Practical techniques to reduce skew and its variations in buffered clock networks
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Combinatorial algorithms for fast clock mesh optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
Proceedings of the 19th international symposium on Physical design
Non-uniform clock mesh optimization with linear programming buffer insertion
Proceedings of the 47th Design Automation Conference
Distributed Resonant clOCK grid Synthesis (ROCKS)
Proceedings of the 48th Design Automation Conference
Minimal buffer insertion in clock trees with skew and slew rate constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Clock meshes are extremely effective at producing low-skew regional clock networks that are tolerant of environmental and process variations. For this reason, clock meshes are used in most high-performance designs, but this robustness consumes significant power. In this work, we present two techniques to optimize high-performance clock meshes. The first technique is a mesh perturbation methodology for nonuniform mesh routing. The second technique is a skew-aware buffer placement through iterative buffer deletion. We demonstrate how these optimizations can achieve significant power reductions and a near elimination of short-circuit power. In addition, the total wire length is decreased, the number of required buffers is decreased, and both skew and robustness are improved on average when variation is considered.