Power optimal buffered clock tree design
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
POPS: A tool for delay/power performance optimization
Journal of Systems Architecture: the EUROMICRO Journal - Modern methods and tools in digital system design
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Multi-objected Optimization in Evolutionary Algorithms Using Satisfiability Classes
Proceedings of the 6th International Conference on Computational Intelligence, Theory and Applications: Fuzzy Days
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Buffer sizing for clock power minimization subject to general skew constraints
Proceedings of the 41st annual Design Automation Conference
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Dynamic thermal clock skew compensation using tunable delay buffers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Mesh-Buffer Displacement Optimization Strategy
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
VLSI Physical Design: From Graph Partitioning to Timing Closure
VLSI Physical Design: From Graph Partitioning to Timing Closure
Crosslink insertion for variation-driven clock network construction
Proceedings of the great lakes symposium on VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
GRIP: Global Routing via Integer Programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An Effective and Efficient Framework for Clock Latency Range Aware Clock Network Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Most engineering problems involve optimizing different and competing objectives. To solve multi-objective problems, normally a weighted sum of the objectives is optimized. However, how the weights are assigned can greatly affect the outcome. Therefore, many designers have to resort to producing the Pareto surface - a time-consuming procedure. In this paper, we propose a framework for solving multi-objective geometric programming problems where weights in the objective are optimally calculated during the optimization problem without having to produce the Pareto surface. It is shown that the proposed self-tuning multi-objective framework can be applied to geometric programming gate sizing problems. Then, the efficacy of the proposed framework is proven using the clock network buffer sizing problem as an application. The problem is first formulated as a geometric programming (GP) problem with the objectives of reducing power, skew, and slew. The problem is solved using ISPD09 circuits. The power, skew and slew of the optimized networks are calculated using ngspice. The results show on average 52% reduction in power and 28% reduction in skew compared to the original networks. The self-tuning multi-objective solution is shown superior to any single objective solution with no impact on runtime.