Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2013 ACM international symposium on International symposium on physical design
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
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Clock meshes are an important resource for high performance circuit designers due to its robustness to variability. Until recently, there were no tools able to support the use of clock meshes in automated synthesis flows. In the last years commercial tools were adapted to support clock meshes [1]and the academia has addressed the problems of clock mesh design automation and optimization. However, current optimization techniques are still very preliminary. Many other aspects of the clock mesh design can be explored besides of edge removal and buffer placement explored by [2] and [3]. This paper proposes an algorithm to move the mesh buffers over the mesh wires to a position that minimizes the clock skew at the clock sinks. Experimental data show significant skew reduction using the algorithm presented in this paper. The clock mesh area and capacitance are unaffected by this strategy, therefore no overhead is introduced.