Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
A practical clock tree synthesis for semi-synchronous circuits
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A fast algorithm for context-aware buffer insertion
Proceedings of the 37th Annual Design Automation Conference
Maze routing with buffer insertion and wiresizing
Proceedings of the 37th Annual Design Automation Conference
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Process variation aware clock tree routing
Proceedings of the 2003 international symposium on Physical design
High-Speed Clock Network Design
High-Speed Clock Network Design
Convex Optimization
Reducing clock skew variability via cross links
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Improved algorithms for link-based non-tree clock networks for skew variability reduction
Proceedings of the 2005 international symposium on Physical design
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Process-induced skew reduction in nominal zero-skew clock trees
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A Mesh-Buffer Displacement Optimization Strategy
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
Cross link insertion for improving tolerance to variations in clock network synthesis
Proceedings of the 2011 international symposium on Physical design
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
VLSI Physical Design: From Graph Partitioning to Timing Closure
VLSI Physical Design: From Graph Partitioning to Timing Closure
Theory and Applications of Robust Optimization
SIAM Review
Multilevel tree fusion for robust clock networks
Proceedings of the International Conference on Computer-Aided Design
On construction low power and robust clock tree via slew budgeting
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
General skew constrained clock network sizing based on sequential linear programming
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Minimizing power and skew for clock networks are critical and difficult tasks which can be greatly affected by buffer sizing. However, buffer sizing is a non-linear problem and most existing algorithms are heuristics that fail to obtain a global minimum. In addition, existing buffer sizing solutions do not usually consider manufacturing variations. Any design made without considering variation can fail to meet design constraints after manufacturing. In this paper, first we proposed an efficient optimization scheme based on geometric programming (GP) for buffer sizing of clock networks. Then, we extended the GP formulation to consider process variations in the buffer sizes using robust optimization (RO). The resultant variation-aware network is examined with SPICE and shown to be superior in terms of robustness to variations while decreasing area, power and average skew.