High-Speed Clock Network Design

Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking

Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Power Grid Planning for Microprocessors and SOCS

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Statistical Analysis of Clock Skew Variation in H-Tree Structure

ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design

Clock skew reduction by self-compensating manufacturing variability with on-chip sensors

Proceedings of the 20th symposium on Great lakes symposium on VLSI

Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Buffer sizing for clock networks using robust geometric programming considering variations in buffer sizes

Proceedings of the 2013 ACM international symposium on International symposium on physical design

Reliability improvement of logic and clock paths in power-efficient designs

ACM Journal on Emerging Technologies in Computing Systems (JETC) - Special Issue on Reliability and Device Degradation in Emerging Technologies and Special Issue on WoSAR 2011