Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Statistical clock skew modeling with data delay variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
High-Speed Clock Network Design
High-Speed Clock Network Design
Interconnect Technology and Design for Gigascale Integration
Interconnect Technology and Design for Gigascale Integration
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Improvement of power distribution network using correlation-based regression analysis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Clock tree synthesis with data-path sensitivity matching
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A case for dynamic frequency tuning in on-chip networks
Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Clock skew optimization considering complicated power modes
Proceedings of the Conference on Design, Automation and Test in Europe
RAFT: A router architecture with frequency tuning for on-chip networks
Journal of Parallel and Distributed Computing
High performance, energy efficiency, and scalability with GALS chip multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock repeater characterization for jitter-aware clock tree synthesis
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Effect of process variations in 3D global clock distribution networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that controls clock skew and power dissipation. In this paper, we evaluate clock skew under several variability models, and demonstrate relationship among clock skew, transition time constraint and power dissipation. Experimental results show that constraint of small transition time reduces clock skew under manufacturing and supply voltage variabilities, whereas there is an optimum constraint value for temperature gradient. Our experiments in a 0.18驴m technology indicate that clock skew is minimized when clock buffer is sized such that the ratio of output and input capacitance is four.