Statistical Analysis of Clock Skew Variation in H-Tree Structure
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Elmore model for energy estimation in RC trees
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Challenges in advanced metallization schemes
Microelectronic Engineering
Robust wiring networks for DfY considering timing constraints
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NoC Communication Strategies Using Time-to-Digital Conversion
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Interconnect lifetime prediction for reliability-aware systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IntSim: A CAD tool for optimization of multilevel interconnect networks
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IBM Journal of Research and Development
Quality factor and frequency bandwidth of 2D self-inductors in 3D integration stacks
Microelectronic Engineering
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
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