Interconnect Technology and Design for Gigascale Integration
Interconnect Technology and Design for Gigascale Integration
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
IBM Journal of Research and Development
Interconnect opportunities for gigascale integration
IBM Journal of Research and Development
Three-dimensional silicon integration
IBM Journal of Research and Development
Workload and network-optimized computing systems
IBM Journal of Research and Development
Complexity dichotomy on partial grid recognition
Theoretical Computer Science
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Three-dimensional (3D) integration technology promises to continue enhancing integrated-circuit system performance with high bandwidth, low latency, low power, and a small form factor for a variety of applications. In this work, conventional C4 (controlled-collapse chip connection) technology is studied for robust interconnection between stacked thin chips. Various solder hierarchies to enable 3D chip stacking and packaging are investigated. Examples are presented to compare stacking schemes with sequential and parallel reflow. Chips as thin as 90 µm are stacked using conventional chip-placement and reflow processes, and the associated process challenges are investigated and discussed. Warpage of the thin chips is measured on various substrates. Rework of the chip stack has also been demonstrated through a temporary chip attachment operation, and the scalability of reworkable C4 is investigated.