Future System-on-Silicon LSI Chips
IEEE Micro
IBM Journal of Research and Development - POWER5 and packaging
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
IBM Journal of Research and Development
Three-dimensional silicon integration
IBM Journal of Research and Development
3D chip stacking with C4 technology
IBM Journal of Research and Development
Confined VLS growth and structural characterization of silicon nanoribbons
Microelectronic Engineering
Characterizing the impact of using spare-cores on application performance
EuroPar'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part I
Hierarchical circuit-switched NoC for multicore video processing
Microprocessors & Microsystems
Complexity dichotomy on partial grid recognition
Theoretical Computer Science
3D CMOS-memristor hybrid circuits: devices, integration, architecture, and applications
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
A software approach for combating asymmetries of non-volatile memories
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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Three-dimensional (3D) integration using through-silicon vias (TSVs) and low-volume lead-free solder interconnects allows the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies. There are several approaches for 3D chip stacking including chip to chip, chip to wafer, and wafer to wafer. Chip-to-chip integration and chip-to-wafer integration offer the ability to stack known good dies, which can lead to higher yields without integrated redundancy. In the future, with structure and process optimization, wafer-to-wafer integration may provide an ultimate solution for the highest manufacturing throughput assuming a high yield and minimal loss of good dies and wafers. In the near term, chip-to-chip and chip-to-wafer integration may offer high yield, high flexibility, and high performance with added time-to-market advantages. In this work, results are reported for 3D integration after using a chip-to-wafer assembly process using 3D chip-stacking technology and fine-pitch interconnects with lead-free solder. Stacks of up to six dies were assembled and characterized using lead-free solder interconnections that were less than 6 µm in height. The average resistance of the TSV including the lead-free solder interconnect was as low as 21 mΩ.