SPAA '92 Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures
Improving locality and parallelism in nested loops
Improving locality and parallelism in nested loops
A superblock-based flash translation layer for NAND flash memory
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
Design of flash-based DBMS: an in-page logging approach
Proceedings of the 2007 ACM SIGMOD international conference on Management of data
Hybrid cache architecture with disparate memory technologies
Proceedings of the 36th annual international symposium on Computer architecture
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
IBM Journal of Research and Development
Compiler-assisted data distribution for chip multiprocessors
Proceedings of the 19th international conference on Parallel architectures and compilation techniques
Operating system support for NVM+DRAM hybrid main memory
HotOS'09 Proceedings of the 12th conference on Hot topics in operating systems
C1C: A configurable, compiler-guided STT-RAM L1 cache
ACM Transactions on Architecture and Code Optimization (TACO)
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The recent advances in non-volatile memory technologies promise the delivery of future high performance and low power computing systems. While these technologies provide attractive features, they exhibit different degrees of asymmetric read/write behavior, resulting in under utilization of the technology benefits in many scenarios. Future systems should be aware of this asymmetry to fully utilize these memory technologies. In this paper, we propose software dispatch, a cross-layer approach to distribute data to appropriate memory resources based on an application's data access characteristics. We demonstrate the application of the proposed technique through a case study system with hybrid memory caches, on which we achieve over 5% performance improvement and 9.8% power savings compared to the state-of-the-art technique.