2.5D system integration: a design driven system implementation schema
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Interconnect delay minimization through interlayer via placement in 3-D ICs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Timing-driven via placement heuristics for three-dimensional ICs
Integration, the VLSI Journal
Multilayer stacking technology using wafer-to-wafer stacked method
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Microelectronic Engineering
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Three-dimensional integration technology and integrated systems
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
A 3D prototyping chip based on a wafer-level stacking technology
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
IBM Journal of Research and Development
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D super chip technology to achieve low-power and high-performance system-on-a chip
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
3D integration for energy efficient system design
Proceedings of the 48th Design Automation Conference
| Hi-index | 0.00 |
A new three-dimensional (3D) integration technology to achieve system-on-silicon LSIs has been proposed. Several LSI wafers are vertically stacked and glued each other after thinning them in this 3D integration technology. Therefore, this technology can be considered as both 3D LSI technology and a wafer-scale 3D chip-on-chip packaging technology. Effective packing density can be significantly increased by stacking several chips in the vertical direction. In addition, a huge number of interconnections are formed through these stacked chips. Therefore, the chip-package co-design considering the 3D distribution of generated heat and the 3D routing of wirings becomes very important to realize 3D LSIs or 3D multichip modules (3D-MCMs) using this new integration technology. Various kinds of new system-on-silicon LSIs or system LSIs based on this 3D integration technology have been proposed. A real time microvision system has been described as a typical example of the systems realized by using this new 3D integration technology. Several key technologies for this 3D integration such as formation of buried interconnection and microbump, wafer thinning, wafer alignment and wafer bonding have been described.