Multilayer stacking technology using wafer-to-wafer stacked method

Authors:
Nobuaki Miyakawa;Eiri Hashimoto;Takanori Maebashi;Natsuo Nakamura;Yutaka Sacho;Shigeto Nakayama;Shinjiro Toyoda
Affiliations:
Honda Research Institute Japan, Saitama, Japan;Honda Research Institute Japan, Saitama, Japan;Honda Research Institute Japan, Saitama, Japan;Honda Research Institute Japan, Saitama, Japan;Honda Research Institute Japan, Saitama, Japan;Honda Research Institute Japan, Saitama, Japan;Honda Research Institute Japan, Saitama, Japan
Venue:
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Year:
2008

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Abstract

We have developed a new three-dimensional stacking technology using the wafer-to-wafer stacked method. Electrical conductivity between each wafer is almost 100% and contact resistance is less than 0.7Ω between a through-silicon via (TSV) and a microbump. We have also created a prototype of a three-layer stacking device using our technology, where each wafer for the stacking is fabricated by using 0.18um CMOS technology based on 8-inch wafers. The device is operated by two times the frequency of the multichip module (MCM) device case using a two-dimensional device with identical functions and minimally different power consumption. The yields obtained from the results comprising all functional tests are over 60%.