Performance Analysis of k-ary n-cube Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
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IEEE/ACM Transactions on Networking (TON)
Performance Guarantees in Communication Networks
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A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Computers
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Proceedings of the 2009 Asia and South Pacific Design Automation Conference
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Advanced integration technologies enable the construction of Network-on-Chip (NoC) from two dimensions to three dimensions. Studies have shown that 3D NoCs can improve average communication performance because of the possibility of using the additional dimension to shorten communication distance. In this paper, we present a detailed case study on worst-case communication performance in regular k-ary-2-mesh networks. Through both analysis and simulation, we show that, while 3D networks achieve better average performance, this may not be the case for worst-case performance mainly due to constraints on vertical channels. Our analysis is based on network calculus, which allows to calculate theoretical delay bounds for constrained flows traversing network elements.