Real-time virtual channel flow control
Journal of Parallel and Distributed Computing
A Priority-Driven Flow Control Mechanism for Real-Time Traffic in Multiprocessor Networks
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Real-Time Systems
Limits on Interconnection Network Performance
IEEE Transactions on Parallel and Distributed Systems
A Real-Time Communication Method for Wormhole Switching Networks
ICPP '98 Proceedings of the 1998 International Conference on Parallel Processing
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Future Generation Computer Systems
Analysis of communication delay bounds for network on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
From 2D to 3D NoCs: a case study on worst-case communication performance
Proceedings of the 2009 International Conference on Computer-Aided Design
Analysis of worst-case delay bounds for on-chip packet-switching networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
Worst-case end-to-end delays evaluation for SpaceWire networks
Discrete Event Dynamic Systems
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
NoC contention analysis using a branch-and-prune algorithm
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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The feasibility of a message in a network concerns if its timing property can be satisfied without jeopardizing any messages already in the network to meet their timing properties. We present a novel feasibility analysis for real-time (RT) and nonreal-time (NT) messages in wormhole-routed networks on chip. For RT messages, we formulate a contention tree that captures contentions in the network. For coexisting RT and NT messages, we propose a simple bandwidth partitioning method that allows us to analyze their feasibility independently.