Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Performance Guarantees in Communication Networks
Performance Guarantees in Communication Networks
Æthereal Network on Chip: Concepts, Architectures, and Implementations
IEEE Design & Test
Feasibility analysis of messages for on-chip networks using wormhole routing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Tight end-to-end per-flow delay bounds in FIFO multiplexing sink-tree networks
Performance Evaluation
Analysis of communication delay bounds for network on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
TDM virtual-circuit configuration for network-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Network calculus: a theory of deterministic queuing systems for the internet
Network calculus: a theory of deterministic queuing systems for the internet
Applying network calculus for performance analysis of self-similar traffic in on-chip networks
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Static timing analysis for modeling QoS in networks-on-chip
Journal of Parallel and Distributed Computing
Worst-case end-to-end delays evaluation for SpaceWire networks
Discrete Event Dynamic Systems
Using Network Calculus to compute end-to-end delays in SpaceWire networks
ACM SIGBED Review - Work-in-Progress (WiP) Session of the 23rd Euromicro Conference on Real-Time Systems (ECRTS 2011)
Modeling SpaceWire networks with network calculus
Proceedings of the 1st International Workshop on Worst-Case Traversal Time
Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Introduction to unmanned spacecraft on-board communications: evolution of timeliness needs
Proceeings of the 2nd International Workshop on Worst-Case Traversal Time
Mathematical formalisms for performance evaluation of networks-on-chip
ACM Computing Surveys (CSUR)
Designing energy-efficient NoC for real-time embedded systems through slack optimization
Proceedings of the 50th Annual Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
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In packet-switched network-on-chip, computing worst-case delay bounds is crucial for designing predictable and cost-effective communication systems but yet an intractable problem due to complicated resource sharing scenarios. For wormhole networks with credit-based flow control, the existence of cyclic dependency between flit delivery and credit generation further complicates the problem. Based on network calculus, we propose a technique for analyzing communication delay bounds for individual flows in wormhole networks. We first propose router service analysis models for flow control, link and buffer sharing. Based on these analysis models, we obtain a buffering-sharing analysis network, which is open-ended and captures both flow control and link sharing. Furthermore, we compute equivalent service curves for individual flows using the network contention tree model in the buffer-sharing analysis network, and then derive their delay bounds. Our experimental results verify that the theoretical bounds are correct and tight.