Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
3-D topologies for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Proceedings of the 2nd international conference on Nano-Networks
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
From 2D to 3D NoCs: a case study on worst-case communication performance
Proceedings of the 2009 International Conference on Computer-Aided Design
An efficient distributed memory interface for many-core platform with 3D stacked DRAM
Proceedings of the Conference on Design, Automation and Test in Europe
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture
Journal of Computer and System Sciences
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As Three Dimensional Integrated Circuits (3D ICs) have been emerging as a viable candidate to achieve better performance and package, combining the benefits of 3D IC and Network-on-Chip (NoC) schemes provides a significant performance gain for 3D architectures. Through-Silicon-Via (TSV), employed for inter-layer connectivity (vertical channel)in 3D ICs, reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs. In this paper, we propose two novel stacked topologies for 3D architectures to reduce the area overhead of TSVs and power dissipation on each layer with minimal performance penalty. The presented schemes benefit of clustering the mesh topology in order to mitigate TSV footprint on each stacked layer.