DATE '00 Proceedings of the conference on Design, automation and test in Europe
Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
A detailed cost model for concurrent use with hardware/software co-design
Proceedings of the 39th annual Design Automation Conference
Nanoelectronics and Information Technology: Advanced Electronic Materials and Novel Devices
Nanoelectronics and Information Technology: Advanced Electronic Materials and Novel Devices
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy
Proceedings of the 43rd annual Design Automation Conference
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Placement of thermal vias in 3-D ICs using various thermal objectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Memory technology for extended large-scale integration in future electronics applications
Proceedings of the conference on Design, automation and test in Europe
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Scalability of network-on-chip communication architecture for 3-D meshes
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
From 2D to 3D NoCs: a case study on worst-case communication performance
Proceedings of the 2009 International Conference on Computer-Aided Design
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
3D GPU architecture using cache stacking: performance, cost, power and thermal analysis
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
IEEE Transactions on Circuits and Systems II: Express Briefs
Cost-aware three-dimensional (3D) many-core multiprocessor design
Proceedings of the 47th Design Automation Conference
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
Testing TSV-based three-dimensional stacked ICs
Proceedings of the Conference on Design, Automation and Test in Europe
SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips
Proceedings of the Conference on Design, Automation and Test in Europe
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Fabrication cost analysis and cost-aware design space exploration for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sunfloor 3D: a tool for networks on chip topology synthesis for 3-D systems on chips
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Equivalent lumped element models for various n-port through silicon vias networks
Proceedings of the 16th Asia and South Pacific Design Automation Conference
HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Journal of Electronic Testing: Theory and Applications
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper
Journal of Electronic Testing: Theory and Applications
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
TSV open defects in 3D integrated circuits: characterization, test, and optimal spare allocation
Proceedings of the 49th Annual Design Automation Conference
Distributed memory interface synthesis for network-on-chips with 3D-stacked DRAMs
Proceedings of the International Conference on Computer-Aided Design
Challenges and emerging solutions in testing TSV-based 2 1/2D- and 3D-stacked ICs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result upto 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them.