Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
3D Integration: Technology and Applications
3D Integration: Technology and Applications
Analysis and Design of Digital Integrated Circuits
Analysis and Design of Digital Integrated Circuits
Test Challenges for 3D Integrated Circuits
IEEE Design & Test
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
ATS '09 Proceedings of the 2009 Asian Test Symposium
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
TSV redundancy: architecture and design issues in 3D IC
Proceedings of the Conference on Design, Automation and Test in Europe
On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Performance Characterization of TSV in 3D IC via Sensitivity Analysis
ATS '10 Proceedings of the 2010 19th IEEE Asian Test Symposium
Cost-Effective TSV Grouping for Yield Improvement of 3D-ICs
ATS '11 Proceedings of the 2011 Asian Test Symposium
RC delay metrics for performance optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Experimental Characterization of CMOS Interconnect Open Defects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On effective and efficient in-field TSV repair for stacked 3D ICs
Proceedings of the 50th Annual Design Automation Conference
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Three-dimensional integration based on die/wafer stacking and through-silicon-vias (TSVs) promises to overcome interconnect bottlenecks for nanoscale integrated circuits (ICs). However, TSVs are prone to defects such as shorts and opens that affect circuit operation in stacked ICs. We analyze the impact of open defects on TSVs and describe techniques for screening such defects. The proposed characterization technique estimates the additional delay introduced due to a resistive open defect as well as due to re-routing based on spare TSVs. We also present an optimization method based on integer linear programming (ILP) that allocates spares to functional TSVs such that the spare for a functional TSV is neither too close to a functional TSV (to avoid the case of both functional and spare TSV being defective) nor too far to ensure that the additional delay due to rerouting is below an upper limit. Results are presented using Hspice simulations based on a 45 nm predictive technology model, recently published data on TSV parasitics, and a commercial ILP solver.