On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits

Authors:
Roshan Weerasekera;Matt Grange;Dinesh Pamunuwa;Hannu Tenhunen
Affiliations:
Lancaster University, Lancaster, UK;Lancaster University, Lancaster, UK;Lancaster University, Lancaster, UK;KTH School of Information and Communication Technologies, Kista, Sweden
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2010

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Abstract

This paper discusses signal integrity (SI) issues and signalling techniques for Through Silicon Via (TSV) interconnects in 3-D Integrated Circuits (ICs). Field-solver extracted parasitics of TSVs have been employed in Spice simulations to investigate the effect of each parasitic component on performance metrics such as delay and crosstalk and identify a reduced-order electrical model that captures all relevant effects. We show that in dense TSV structures voltage-mode (VM) signalling does not lend itself to achieving high data-rates, and that current-mode (CM) signalling is more effective for high throughput signalling as well as jitter reduction. Data rates, energy consumption and coupled noise for the different signalling modes are extracted.