A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

Authors:
Rizwan Bashirullah;Wentai Liu;Ralph Cavin;Dale Edwards
Affiliations:
Department of Electrical and Computer Engineering, University of Florida, Gainsville, FL and Department of Electrical Engineering, North Carolina State University, Raleigh NC;School of Engineering, University of California at Santa Cruz, Santa Cruz, CA;Semiconductor Research Corporation, Research Triangle Park, NC;Semiconductor Research Corporation, Research Triangle Park, NC
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2004

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Abstract

This brief describes an adaptive bandwidth bus architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode (CM) signaling. An experimental adaptive bandwidth bus test chip fabricated in AMI 1.6-µm Bulk CMOS indicates a reduction in power dissipation of approximately 62% over CM sensing and an increase in maximum data rate of 40% over voltage-mode signaling.