Current-mode signaling in deep submicrometer global interconnects

Authors:
Rizwan Bashirullah;Wentai Liu;Ralph K. Cavin, III
Affiliations:
Department of Electrical Engineering, North Carolina State University, Raleigh NC;Department of Electrical Engineering, North Carolina State University, Raleigh NC and Department of Electrical Engineering, University of California, Santa Cruz, CA;Semiconductor Research Corporation, Research Triangle Park NC
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Year:
2003

Citing 3
Cited 9

Power considerations in the design of the Alpha 21264 microprocessor

DAC '98 Proceedings of the 35th annual Design Automation Conference
Digital systems engineering

Digital systems engineering
Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor

ISPD '00 Proceedings of the 2000 international symposium on Physical design

Simplified delay design guidelines for on-chip global interconnects

Proceedings of the 14th ACM Great Lakes symposium on VLSI
A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Three-dimensional Integrated Circuit Design

Three-dimensional Integrated Circuit Design
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Asynchronous current mode serial communication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

Microprocessors & Microsystems
Semi-serial on-chip link implementation for energy efficiency and high throughput

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling of energy dissipation in RLC current-mode signaling

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures

ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper addresses propagation delay and power dissipation for current mode signaling in deep submicrometer global interconnects. Based on the effective lumped element resistance and capacitance approximation of distributed RC lines, simple yet accurate closed-form expressions of delay and power dissipation are presented. A new closed-form solution of delay under step input excitation is first developed, exhibiting an accuracy that is within 5% of SPICE simulations for a wide range of parameters. The usefulness of this solution is that resistive load termination for current mode signaling is accurately modeled. This model is then extended to a generalized delay formulation for ramp inputs with arbitrary rise time. Using these expressions, the optimum-line width that minimizes the total delay for current mode circuits is found. Additionally, a new power-dissipation model for current-mode signaling is developed to understand the design tradeoffs between current and voltage sensing. Based on the results and derived formulations, a comparison between voltage and current mode repeater insertion for long global deep submicrometer interconnects is presented.