Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 37th Annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects
ISVLSI '03 Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03)
Current-mode signaling in deep submicrometer global interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
A Crosstalk Aware Interconnect with Variable Cycle Transmission
Proceedings of the conference on Design, automation and test in Europe - Volume 1
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DVS for On-Chip Bus Designs Based on Timing Error Correction
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A novel buffer circuit for energy efficient signaling in dual-VDD systems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A dual-VDD boosted pulsed bus technique for low power and low leakage operation
Proceedings of the 2006 international symposium on Low power electronics and design
Thermal Impacts on NoC Interconnects
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Variation tolerant NoC design by means of self-calibrating links
Proceedings of the conference on Design, automation and test in Europe
Transition skew coding for global on-chip interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A flexible parallel simulator for networks-on-chip with error control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
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This paper presents a novel adaptive voltage scheme based on a lookahead circuit that checks the transmitter buffer for data transitions. The advanced knowledge of incoming data patterns is used to adjust the link swing voltage, improving delay and energy performance. In the presented example system, a transition detection circuit is used to check the transmitter buffer for rising transitions (‘0’ in cycle t, ‘1’ in cycle t+1). When a rising transition is detected, a higher supply voltage is applied to the driver for a small portion of the clock cycle to boost the rising edge delay, improving link performance. A lower voltage is used for all other transmissions, improving the delay performance of falling edge transitions and the link energy dissipation. For a 1 GHz link frequency, the proposed approach improves energy dissipation by 45% compared to a traditional two-inverter buffer. An energy savings of up to 15% is achieved compared to a previously proposed dual-voltage scheme.