Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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We consider the power-optimal design of dual-VT CMOScircuits under challenging delay constraints, with thresholdvoltages and device sizes as design variables. We show thatthe presence of interconnect resistance affects the optimumchoices of VT and device sizes, and that ignoring the resistance can lead to highly suboptimal results. We also presentcriteria for deciding when interconnect resistance should betaken into account.