Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The scaling challenge: can correct-by-construction design help?
Proceedings of the 2003 international symposium on Physical design
A new algorithm for improved VDD assignment in low power dual VDD systems
Proceedings of the 2004 international symposium on Low power electronics and design
A novel buffer circuit for energy efficient signaling in dual-VDD systems
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Linear programming for sizing, Vth and Vdd assignment
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A robust edge encoding technique for energy-efficient multi-cycle interconnect
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Energy efficiency bounds of pulse-encoded buses
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A robust edge encoding technique for energy-efficient multi-cycle interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we propose a new dual-VDD bus technique that is well suited for low power operation. This technique adapts a static pulsed bus architecture to use dual-VDD power supplies. During quiescent periods, the bus system idles at the lower of the two VDD supplies, thereby lowering static power dissipation. When actively transitioning, the inverters in the bus system are temporarily boosted to the higher VDD supply to provide the needed drive strength for performance. Since the VDD boosting is done in a pulsed manner, the bus system is in a high VDD state only when required, ensuring lower power operation without sacrificing performance. This technique yields up to a 50% reduction in total power over traditional static buses and up to a 35% reduction in total power over standard static pulsed buses, with a 12-15% delay improvement.