Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Modeling and analysis of differential signaling for minimizing inductive cross-talk
Proceedings of the 38th annual Design Automation Conference
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect Optimization Strategies for High-Performance VLSI Designs
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A dual-VDD boosted pulsed bus technique for low power and low leakage operation
Proceedings of the 2006 international symposium on Low power electronics and design
Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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We propose a novel buffer circuit that allows on-chip signaling for dual-VDD systems at the lower supply (VDDL) with a higher performance and smaller area than the standard buffer. The proposed dual-VDD buffer uses a pull-up PMOS connected to the higher supply (VDDH) rail in parallel with a standard buffer connected to VDDL. The VDDH pull-up PMOS turns on only briefly during a rising transition to aid the VDDL pull-up PMOS but avoids contention at steady state. The higher current drive with the VDDH PMOS allows a favorable trade-off of a considerable reduction in the VDDL buffer size for a small increase in the VDDH PMOS size. This trade-off is especially useful for meeting aggressive delay targets with the lower supply and allows the dual-VDD buffer to increase performance (up to 22%) compared to the standard buffer at VDDL, while still consuming less energy than VDDH signaling. The dual-VDD buffer also achieves gains in energy (up to 17%), buffer area (up to 56%) and peak current (up to 33%) at delay targets that can be met with standard buffers using VDDL.