Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Level conversion for dual-supply systems
Proceedings of the 2003 international symposium on Low power electronics and design
Interconnect-power dissipation in a microprocessor
Proceedings of the 2004 international workshop on System level interconnect prediction
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing total power by simultaneous Vdd/Vth assignment
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Linear programming for sizing, Vth and Vdd assignment
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Power distribution techniques for dual VDD circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A dual-VDD boosted pulsed bus technique for low power and low leakage operation
Proceedings of the 2006 international symposium on Low power electronics and design
Voltage island aware floorplanning for power and timing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal voltage assignment approach for low power using ILP
WSEAS Transactions on Circuits and Systems
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Optimal dual voltage assignment algorithm for low power under timing-constraints
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Register allocation for high-level synthesis using dual supply voltages
Proceedings of the 46th Annual Design Automation Conference
Voltage-Island partitioning and floorplanning under timing constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Parametric yield driven resource binding in behavioral synthesis with multi-Vth/Vdd library
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Network flow-based simultaneous retiming and slack budgeting for low power design
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Low power and high speed multi threshold voltage interface circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
| Hi-index | 0.00 |
We present the first in-depth study of the two existing algorithms, namely, Clustered Voltage Scaling (CVS) and Extended Clustered Voltage Scaling (ECVS), used for assigning the voltage supply to gates in integrated circuits having dual power supplies. We present a comparison of the achievable power savings using these algorithms on various benchmark circuits and first point out that ECVS does provide appreciably larger power improvements compared to CVS. We then provide a new algorithm based on ECVS that further improves the power savings by efficient assignment of the power supplies to the gates. Our new algorithm provides up to 66% power reduction and improves the power savings by up to 28% and 13% with respect to CVS and ECVS respectively. Furthermore, since level conversion is an essential component of dual power supply systems we also present the first circuit-specific sensitivity study of achievable power savings to the energy and delay penalties imposed by level conversion.