Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 international symposium on Low power electronics and design
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A new algorithm for improved VDD assignment in low power dual VDD systems
Proceedings of the 2004 international symposium on Low power electronics and design
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A dual-VDD boosted pulsed bus technique for low power and low leakage operation
Proceedings of the 2006 international symposium on Low power electronics and design
Low-power FinFET circuit synthesis using multiple supply and threshold voltages
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Total Power Optimization for Combinational Logic Using Genetic Algorithms
Journal of Signal Processing Systems
A new algorithm for simultaneous gate sizing and threshold voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power FinFET circuit synthesis using surface orientation optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Gate sizing and device technology selection algorithms for high-performance industrial designs
Proceedings of the International Conference on Computer-Aided Design
The ISPD-2012 discrete cell sizing contest and benchmark suite
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Discrete sizing for leakage power optimization in physical design: A comparative study
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
ECO cost measurement and incremental gate sizing for late process changes
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
Sensitivity-guided metaheuristics for accurate discrete gate sizing
Proceedings of the International Conference on Computer-Aided Design
An improved benchmark suite for the ISPD-2013 discrete cell sizing contest
Proceedings of the 2013 ACM international symposium on International symposium on physical design
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Most circuit sizing tools calculate the tradeoff between each gate's delay and power or area, and then greedily change the gate with the best tradeoff. We show this is suboptimal. Instead we use a linear program to minimize circuit power. The linear program provides a fast and simultaneous analysis of how each gate affects gates it has a path to. Our approach reduces power by up to 30% compared to commercial software, with a 0.13um library. The runtime for posing and solving the linear program scales linearly with circuit size