Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design

Authors:
Ashish Srivastava;Dennis Sylvester;David Blaauw
Affiliations:
-;-;-
Venue:
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Year:
2004

Citing 2
Cited 12

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Abstract

We present a sensitivity based algorithm for total power including dynamic and subthreshold leakage power minimization using simultaneous sizing, Vdd and Vth assignment. The proposed algorithm is implemented and tested on a set of combinational benchmark circuits. Acomparison with traditional CVS based algorithms demonstrates the advantage of the algorithm including an average power reduction of 37% at primary input activities of 0.1. We also investigate the impact of various low Vdd values on total power savings.