Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Multi-Domain Clock Skew Scheduling
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Low power design using dual threshold voltage
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Probabilistic dual-Vth leakage optimization under variability
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
ExtensiveSlackBalance: an approach to make front-end tools aware of clock skew scheduling
Proceedings of the 43rd annual Design Automation Conference
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Skewed flip-flop transformation for minimizing leakage in sequential circuits
Proceedings of the 44th annual Design Automation Conference
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Proceedings of the 45th annual Design Automation Conference
A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
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Dual-Vth technique is a mature and effective method for reducing leakage power consumption. Previously proposed algorithms assign logic gates with sufficient timing slack to high threshold voltage to reduce leakage power without impact on timing. Meanwhile, clock skew scheduling algorithms are always utilized to optimize period or timing slack. In order to further reduce subthreshold leakage power consumption, in this paper, we ingeniously combine dual voltage assignment technique with intended clock skew scheduling: First, a leakage weight based clock skew scheduling algorithm is proposed to enlarge the leakage power optimization potential. Then we employ a dual-threshold voltage assignment algorithm to minimize leakage power. The experimental results on ISCAS89 benchmark circuits show that, within only several seconds, the leakage power can be further reduced by as much as 41.30% and by 9.87% on average with this new approach, compared to using the traditional method without considering clock skews. Three timing optimized industrial circuit blocks, among which each has around one hundred thousand gates, have also been optimized. It is shown that an average leakage power reduction of 9.95% can be achieved within minutes compared with traditional techniques.