IEEE Transactions on Computers
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Timing optimization through clock skew scheduling
Timing optimization through clock skew scheduling
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 international symposium on Low power electronics and design
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Synthesis of nonzero clock skew circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Dual-Vth leakage reduction with fast clock skew scheduling enhancement
Proceedings of the Conference on Design, Automation and Test in Europe
Inversed temperature dependence aware clock skew scheduling for sequential circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Low power discrete voltage assignment under clock skew scheduling
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinational blocks to be used by slower blocks to meet a more stringent clock cycle time. Instead, we can leverage on the borrowed time to achieve leakage power reduction during gate sizing and/or dual Vth assignment. In this paper, we present the first approach to the best of our knowledge for integrating clock skew scheduling, threshold voltage assignment, and gate sizing into one optimization formulation. Over 29 circuits in the ISCAS89 benchmark suite, this integrated approach can reduce leakage power by as much as 55.83% and by 18.79% on average, compared to using combinational circuit based power optimization on each combinational block without considering clock skews. Using a 65nm dual Vth technology library, this corresponds to a 23.87% peak reduction (6.15% on average) in total power at the ambient operating temperature. The average total power reduction further increases to 9.83% if the high temperature library of the same process technology is used.