A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area

Authors:
Weitong Chuang;Sachin S. Sapatnekar;Ibrahim N. Hajj
Affiliations:
Coordinated Science Laboratory and Dept. of Electrical & Computer Engineering, University of Illinois at Urbana-Champaign;Department of Electrical Engineering and Computer Engineering, Iowa State University;Coordinated Science Laboratory and Dept. of Electrical & Computer Engineering, University of Illinois at Urbana-Champaign
Venue:
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Year:
1993

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