Delay and area optimization in standard-cell design
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Computing optimal clock schedules
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Identification of critical paths in circuits with level-sensitive latches
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Cell based performance optimization of combinational circuits
EURO-DAC '90 Proceedings of the conference on European design automation
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A simple extension of the critical path method is presented which allows more accurate optimization of circuits with level-sensitive latches. The extended formulation provides a sufficient set of constraints to ensure that, when all slacks are non-negative, the corresponding circuit will be free of late signal timing problems. Cycle stealing is directly permitted by the formulation. However, moderate restrictions may be necessary to ensure that the timing constraint graph is acyclic. Forcing the constraint graph to be acyclic allows a broad range of existing optimization algorithms to be easily extended to better optimize circuits with level-sensitive latches. We describe the extension of two such algorithms, both of which attempt to solve the problem of selecting parts from a library to minimize area subject to a cycle time constraint.