Graph algorithms and NP-completeness
Graph algorithms and NP-completeness
Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Hierarchical design based on a calculus of nets
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
On the Construction of Optimal Time Adders (Extended Abstract)
STACS '88 Proceedings of the 5th Annual Symposium on Theoretical Aspects of Computer Science
Delay and power optimization in VLSI circuits
DAC '84 Proceedings of the 21st Design Automation Conference
Optimization of critical paths in circuits with level-sensitive latches
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
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Performance optimization, i.e. the problem of finding an optimal investment of transistor area which meets given delay constraints, is considered from an abstract, cell based point of view which allows only solutions within a discrete solution space of coarse granularity. The main advantages of this problem modelling are the independence of the methods from concrete delay modelling (and thus from technology) and the applicability to even very restrictive design styles (as for example gate arrays or sea of gates). The paper contains a classification of the computational complexity of the performance optimization problem as well as efficient algorithms (where they exist), heuristics and experimental results.