Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization

Authors:
Harsha Sathyamurthy;Sachin S. Sapatnekar;John P. Fishburn
Affiliations:
Mentor Graphics, 1001 Ridder Park Drive, San Jose, CA;Department of ECE, Iowa State University, Ames, IA;AT&T Bell Laboratories, 600 Mountain Avenue, Murray Hill, NJ
Venue:
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Year:
1995

Citing 4
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Abstract

Abstract: An algorithm for unifying the techniques of gate sizing and clock skew optimization for acyclic pipelines is presented. In the design of circuits under very tight timing specifications, the area overhead of gate sizing can be considerable. The procedure utilizes the idea of cycle-borrowing using clock skew optimization to relax the stringency of the timing specification on the critical stages of the pipeline. Experimental results verify that cycle-borrowing using sizing+skew results in a better overall area-delay tradeoff than with sizing alone.