Minimum padding to satisfy short path constraints

A fresh look at retiming via clock skew optimization

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Asymptotically efficient retiming under setup and hold constraints

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Buffer Assignment Algorithms on Data Driven ASICs

IEEE Transactions on Computers

Marsh: min-area retiming with setup and hold constraints

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

Minimum delay optimization for domino logic circuits---a coupling-aware approach

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Clock Period Minimization of Non-Zero Clock Skew Circuits

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

A new approach for integration of min-area retiming and min-delay padding for simultaneously addressing short-path and long-path constraints

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Delay insertion method in clock skew scheduling

Proceedings of the 2005 international symposium on Physical design

Race-condition-aware clock skew scheduling

Proceedings of the 42nd annual Design Automation Conference

Exploiting level sensitive latches in wire pipelining

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

Simultaneous short-path and long-path timing optimization for FPGAs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

An efficient retiming algorithm under setup and hold constraints

Proceedings of the 43rd annual Design Automation Conference

Clock skew scheduling with race conditions considered

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Design of rotary clock based circuits

Proceedings of the 44th annual Design Automation Conference

Clock period minimization with minimum delay insertion

Proceedings of the 44th annual Design Automation Conference

Synthesis of a novel timing-error detection architecture

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits

Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design

Protecting digital circuits against hold time violation due to process variability

Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes

Retiming and time borrowing: optimizing high-performance pulsed-latch-based circuits

Proceedings of the 2009 International Conference on Computer-Aided Design

Multi-level clustering for clock skew optimization

Proceedings of the 2009 International Conference on Computer-Aided Design

Pulse width allocation and clock skew scheduling: optimizing sequential circuits based on pulsed latches

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

A unified online fault detection scheme via checking of stability violation

Proceedings of the Conference on Design, Automation and Test in Europe

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network

Proceedings of the Conference on Design, Automation and Test in Europe

Statistical analysis of hold time violations

Journal of Computational Electronics

Re-synthesis for cost-efficient circuit-level timing speculation

Proceedings of the 48th Design Automation Conference

Fast statistical timing analysis for circuits with post-silicon tunable clock buffers

Proceedings of the International Conference on Computer-Aided Design

Low-power timing closure methodology for ultra-low voltage designs

Proceedings of the International Conference on Computer-Aided Design