IEEE Transactions on Computers
Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Lowering power consumption in clock by using globally asynchronous locally synchronous design style
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low-power clock distribution using multiple voltages and reduced swings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integrated placement and skew optimization for rotary clocking
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Implementing multiphase resonant clocking on a finite-impulse response filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sparse-rotary oscillator array (SROA) design for power and skew reduction
Proceedings of the Conference on Design, Automation and Test in Europe
ZeROA: zero clock skew rotary oscillatory array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Rotary clock technique has been shown to reduce the power dissipation of clock distribution by up to 80%. However, to our knowledge, no practical digital synchronous circuit has been designed that utilizes the rotary technique due to the multi-phase nature of rotary clock signals and the strong coupling between a rotary clock network and the circuit it drives. In this paper, we make the first attempt to design rotary based circuit by proposing a unified clock and circuit design methodology. Given a sequential circuit and a clock frequency, our scheme derives a rotary clock network and a functionally equivalent circuit so that they can be integrated to operate reliably at the target frequency. We have applied our scheme to design several rotary clock based DSP modules. Simulation results show that all designs operate correctly with no timing violation. Compared with designs using conventional clock trees, our designs achieve an average clock power saving of more than 70%.