IEEE Transactions on Computers
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
A clustering-based optimization algorithm in zero-skew routings
DAC '93 Proceedings of the 30th international Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Cycle time and slack optimization for VLSI-chips
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clock Scheduling and Clocktree Construction for High Performance ASICS
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Navigating registers in placement for clock network minimization
Proceedings of the 42nd annual Design Automation Conference
Power Analysis of Rotary Clock
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
A clock power model to evaluate impact of architectural and technology optimizations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gated clock routing for low-power microprocessor design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of rotary clock based circuits
Proceedings of the 44th annual Design Automation Conference
Integrated placement and skew optimization for rotary clocking
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock distribution scheme using coplanar transmission lines
Proceedings of the conference on Design, automation and test in Europe
Custom topology rotary clock router with tree subnetworks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Implementing multiphase resonant clocking on a finite-impulse response filter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-performance, low-power resonant clocking
Proceedings of the International Conference on Computer-Aided Design
Sparse-rotary oscillator array (SROA) design for power and skew reduction
Proceedings of the Conference on Design, Automation and Test in Europe
ZeROA: zero clock skew rotary oscillatory array
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The clock distribution network is a key component on any synchronous VLSI design. As techonology moves into the nanometer era, innovative clocking techniques are required to solve the power dissipation and variability issues. Rotary clocking is a novel technique which employs unterminated rings formed by differential transmission lines to save power and reduce skew variability. Despite its appealing advantages, rotary clocking requires latch locations to match pre-designed clock skew on rotary clock rings. This requirement is a difficult chicken-and-egg problem which prevents its wide application. In this work, we proposed an integrated placement and skew scheduling methodology to break this hurdle, making rotary clocking compatible with practical design flows. A network flow based latch assignment algorithm and a cost-driven skew optimization algorithm are developed. Experiments show that our method can generate chip placements which satisfy the unique requirements of rotary clocks, without sacrificing design quality. By enabling concurrent clock network and placement design, our method can also be applied in other clocking methodologies as well.